Re: [myhdl-list] Re: MyHDL success

[Tom D. <td...@di...>]

Jan,

As far as VHDL goes, for us conversion would be fine. We would only use 
it for delivery to clients so they could synthesize and simulate the design.

Thanks, Tom


Jan Decaluwe wrote:

> bedros wrote:
>
>> agree, Jan did a great job on MyHDL. I've been using
>> it for several months now to verify my ideas before
>> start coding in VHDL.
>
>
> Excellent, that's exactly what MyHDL usage should be all
> about. Now, the VHDL coding, is that for synthesis? If
> it is, would Verilog (and therefore conversion from MyHDL
> code to Verilog) be an option instead?
>
>> I also got it to work with code coverage utility
>> (coverage.py)
>
>
> Good to hear. Does this work better than trace.py?
> I haven't use any of the two, but I noticed that trace.py
> is a standard (though undocumented) unlibrary module.
>
> Regards, Jan
>