[myhdl-list] Re: MyHDL success

[Jan D. <ja...@ja...>]

Frank Palazzolo wrote:
> Jan,
> 
> Just wanted to drop a line and say that MyHDL is working great for me!  I'm
> doing a CPLD design for a switching power-supply controller, and I just got
> both the simulation and verilog generation working flawlessly.  I'm
> targetting the Xilinx XC9536, but testing with a Xilinx SpartanIIE-based
> FPGA board.

Good to hear. Looks like you're the first one I know of to finish a complete
design to implementation with MyHDL. If you would be interested in writing a
small success story (to put on a website, or post to a newsgroup), let me know.

> I only ran into one wishlist item.  It might be nice to have a mechanism to
> put comments into the generated verilog via python.  At first, I thought
> that could mean simply reading the doc information from the generators and
> adding that as comments in the verilog.  But, with some of the naming
> changes that occur, that might be confusing.  You might want to have some
> kind of dedicated verilog_comment() construct instead.

Could you comment on exactly what would be the purpose? I see the Verilog
code merely as a back-end format, not necessarily friendly to human readers.
Is it just to recognize where the code came from? Rewriting the doc-string
should be easy.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
    Python is fun, and now you can design hardware with it:
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