Re: [myhdl-list] MyHDL success

[bedros <be...@ya...>]

agree, Jan did a great job on MyHDL. I've been using
it for several months now to verify my ideas before
start coding in VHDL.

I also got it to work with code coverage utility
(coverage.py)

if you need wave viewer, try GTKwave. They got
binaries for linux and windows. you can get it from
freshmeat.net or the windows bin here
http://www.geocities.com/SiliconValley/Campus/3216/GTKWave/gtkwave-win32.html



--- Frank Palazzolo <pal...@co...> wrote:
> 
> Jan,
> 
> Just wanted to drop a line and say that MyHDL is
> working great for me!  I'm
> doing a CPLD design for a switching power-supply
> controller, and I just got
> both the simulation and verilog generation working
> flawlessly.  I'm
> targetting the Xilinx XC9536, but testing with a
> Xilinx SpartanIIE-based
> FPGA board.
> 
> I only ran into one wishlist item.  It might be nice
> to have a mechanism to
> put comments into the generated verilog via python. 
> At first, I thought
> that could mean simply reading the doc information
> from the generators and
> adding that as comments in the verilog.  But, with
> some of the naming
> changes that occur, that might be confusing.  You
> might want to have some
> kind of dedicated verilog_comment() construct
> instead.
> 
> At any rate, you really can design and simulate
> hardware with Python!
> Thanks for a fantastic tool! :)
> 
> -Frank
> 
> 
> 
> 
>
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