[myhdl-list] MyHDL success

[Frank P. <pal...@co...>]

Jan,

Just wanted to drop a line and say that MyHDL is working great for me!  I'm
doing a CPLD design for a switching power-supply controller, and I just got
both the simulation and verilog generation working flawlessly.  I'm
targetting the Xilinx XC9536, but testing with a Xilinx SpartanIIE-based
FPGA board.

I only ran into one wishlist item.  It might be nice to have a mechanism to
put comments into the generated verilog via python.  At first, I thought
that could mean simply reading the doc information from the generators and
adding that as comments in the verilog.  But, with some of the naming
changes that occur, that might be confusing.  You might want to have some
kind of dedicated verilog_comment() construct instead.

At any rate, you really can design and simulate hardware with Python!
Thanks for a fantastic tool! :)

-Frank