[myhdl-list] Re: inout signals and cosimulation
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From: Jan D. <ja...@ja...> - 2004-03-31 16:24:55
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Jan Decaluwe wrote: > Terry Brown wrote: >> Would you be willing to provide a bug report on Cver? I can do it, >> but since it is myhdl that stimulates the problem, I don't really know >> much about it. > > Yes, but in that case I'd prefer to work on it further to narrow the > problem down and see if I can find more info (in the source for example). This has been fun. When trying to nail down the issue with a small example (without myhdl), I couldn't get it to fail. Then I went back to the original code and tried all kind of changes, but still couldn't get it to work. My final (desperate) move was to remove the $dumpvars call. Suddenly the events appeared at the MyHDL side! So the bug is clearly with cver, in that a $dumpvars call changes the behavior of value change callbacks on wires. I've reproduced this in my small example and will file a bug report. Regards, Jan -- Jan Decaluwe - Resources bvba - http://jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Python is fun, and now you can design hardware with it: http://jandecaluwe.com/Tools/MyHDL/Overview.html |