Re: [myhdl-list] Re: inout signals and cosimulation

[Jan D. <ja...@ja...>]

Terry Brown wrote:

> Fascinating result.  Apparently the problem is in the PLI stuff for 
> cver, since the actual simulation does trigger and shows all expected 
> changes to pp_db_fromsim.

Correct.

> Would you be willing to provide a bug report on Cver?  I can do it, but 
> since it is myhdl that stimulates the problem, I don't really know much 
> about it.

Yes, but in that case I'd prefer to work on it further to narrow the
problem down and see if I can find more info (in the source for example).
Just dumping the database and expecting them to install myhdl for this
is probably not going to be very succesful. So this will take some time.
Is there a good bug tracking system for cver and are they responsive?

In the mean time, I hope you can confirm that the workaround works for
you. (Anyway "explicit is better then implicit" - the Zen of Python :-))

> It's interesting that you get iverilog to work on this.  Could you post 
> the commandline you used for the CoSimulation?  I had been unable to 
> build iverilog for some time under Cygwin, but recently built the 
> verilog-20040220 snapshot.  Although it builds and installs without 
> error, when I run it it either coredumps or complains that it can't find 
> the configuration file, then doesn't accept the -C argument listed in 
> the man page to solve this.  Previous times I have tried Icarus, I have 
> found it unable to compile my designs, primarily because of Xilinx 
> library problems.

As I'm on Linux, I used a different commandline for cver also:

cosim = Cosimulation("cver +loadvpi=./myhdl_vpi:vpi_compat_bootstrap -f manifest ",**globals())

For Icarus (snapshot 20031009), I used:

cmd = "iverilog -o g2board -c manifest"
os.system(cmd)
cosim = Cosimulation("vvp -m ./myhdl.vpi g2board", **globals())

Regards, Jan

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Jan Decaluwe - Resources bvba - http://jandecaluwe.com
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