[myhdl-list] Re: inout signals and cosimulation

[Terry B. <tt...@ve...>]

Jan Decaluwe wrote:
> Terry Brown wrote:
> 
>> Well, it does describe the problem, but I don't think the delay you 
>> refer to is the problem.  This delay was added in an attempt to define 
>> and understand the problem.  I wanted to move the position of the 
>> signal around to be sure I was sampling at the right time with the 
>> print statement.  The problem originated with this delay present.  
>> And, although I understand this problem is with myhdl, is there any 
>> difference in behavior with cver as opposed to icarus?  I am using cver.
>>
>> For what it's worth, using that delay does indeed move the signal as 
>> expected but I still don't see it in myhdl.
>>
>> I also had tried sampling the signal within myhdl at the negative edge 
>> of clock and had no luck.
>>
>> I removed the delay and also removed a ram model which contained 
>> delays from the verilog simulation and I still get the same 
>> problem--the signal doesn't make it across the interface
> 
> 
> Terry:
> 
> I used the code you sent me privately and I think I found the culprit, by
> using an alternative Verilog description and also trying it with Icarus.
> In short, Icarus always does what I expect but cver does not.
> 
> Where you had:
> 
> wire [31:0] pp_db_fromsim;
> assign pp_db_fromsim = (pp_oe) ? 32'hbadda000 : pp_db;
> 
> I also tried the supposedly equivalent (but more explicit):
> 
> reg [31:0] pp_db_fromsim;
> always @(pp_oe or pp_db)
>    pp_db_fromsim = (pp_oe) ? 32'hbadda000 : pp_db;
> 
> As you noticed, pp_db_fromsim doesn't trigger in MyHDL with the first case
> and cver. However, with the second case, it does. With Icarus, it triggers
> with the 2 cases, with identical output.
> 
> At this point, I would conclude that the bug is with cver in that it
> gets the first case wrong. I don't know whether it's because of the
> wire (this would be surprizing) or because of the assign (this also).
> But you never know with the PLI, quite literally.
> 
> Regards, Jan
> 

Fascinating result.  Apparently the problem is in the PLI stuff for 
cver, since the actual simulation does trigger and shows all expected 
changes to pp_db_fromsim.

Would you be willing to provide a bug report on Cver?  I can do it, but 
since it is myhdl that stimulates the problem, I don't really know much 
about it.

It's interesting that you get iverilog to work on this.  Could you post 
the commandline you used for the CoSimulation?  I had been unable to 
build iverilog for some time under Cygwin, but recently built the 
verilog-20040220 snapshot.  Although it builds and installs without 
error, when I run it it either coredumps or complains that it can't find 
the configuration file, then doesn't accept the -C argument listed in 
the man page to solve this.  Previous times I have tried Icarus, I have 
found it unable to compile my designs, primarily because of Xilinx 
library problems.

I have yet to find anything Cver doesn't handle (except this :)

Thanks for the help

Terry