[myhdl-list] Re: inout signals and cosimulation
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From: Jan D. <ja...@ja...> - 2004-03-30 12:45:08
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Terry Brown wrote: > Well, it does describe the problem, but I don't think the delay you > refer to is the problem. This delay was added in an attempt to define > and understand the problem. I wanted to move the position of the signal > around to be sure I was sampling at the right time with the print > statement. The problem originated with this delay present. And, > although I understand this problem is with myhdl, is there any > difference in behavior with cver as opposed to icarus? I am using cver. > > For what it's worth, using that delay does indeed move the signal as > expected but I still don't see it in myhdl. > > I also had tried sampling the signal within myhdl at the negative edge > of clock and had no luck. > > I removed the delay and also removed a ram model which contained delays > from the verilog simulation and I still get the same problem--the signal > doesn't make it across the interface Terry: I used the code you sent me privately and I think I found the culprit, by using an alternative Verilog description and also trying it with Icarus. In short, Icarus always does what I expect but cver does not. Where you had: wire [31:0] pp_db_fromsim; assign pp_db_fromsim = (pp_oe) ? 32'hbadda000 : pp_db; I also tried the supposedly equivalent (but more explicit): reg [31:0] pp_db_fromsim; always @(pp_oe or pp_db) pp_db_fromsim = (pp_oe) ? 32'hbadda000 : pp_db; As you noticed, pp_db_fromsim doesn't trigger in MyHDL with the first case and cver. However, with the second case, it does. With Icarus, it triggers with the 2 cases, with identical output. At this point, I would conclude that the bug is with cver in that it gets the first case wrong. I don't know whether it's because of the wire (this would be surprizing) or because of the assign (this also). But you never know with the PLI, quite literally. Regards, Jan -- Jan Decaluwe - Resources bvba - http://jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Python is fun, and now you can design hardware with it: http://jandecaluwe.com/Tools/MyHDL/Overview.html |