[myhdl-list] Re: inout signals and cosimulation
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From: Jan D. <ja...@ja...> - 2004-03-29 17:28:49
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Terry Brown wrote: > Well, it does describe the problem, but I don't think the delay you > refer to is the problem. This delay was added in an attempt to define > and understand the problem. I wanted to move the position of the signal > around to be sure I was sampling at the right time with the print > statement. The problem originated with this delay present. And, > although I understand this problem is with myhdl, is there any > difference in behavior with cver as opposed to icarus? I am using cver. > Terry: Would it be possible to send me the (relevant part of the) source code - at this point I would need that to understand the cause of the problem. Thanks - Jan -- Jan Decaluwe - Resources bvba - http://jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Python is fun, and now you can design hardware with it: http://jandecaluwe.com/Tools/MyHDL/Overview.html |