[myhdl-list] Re: Conversion to VHDL in plan?

[Jan D. <ja...@ja...>]

Guenter Dannoritzer wrote:
> Hello Jan,
> 
> I was wondering whether you plan to add a conversion of MyHDL code to 
> VHDL, similar to the Verilog conversion?

Short answer: I would like to support VHDL (cosimulation, conversion)
but I have currently no plans to work on it myself.

Sponsored interest might change my priorities. Here are my other
considerations on this issue.

First, there is the practical problem of not having an "Icarus VHDL",
that is, a free or open-source VHDL simulator with PLI support that
runs under Linux. Before doing conversion, we first need cosimulation
for verfication.

Secondly, my main goal with conversion to Verilog is to have a path
to implementation. Verilog is used as a back-end language, that many
other EDA tools understand - even in organizations where front-end
design is done with VHDL. My principal goal with conversion is to lower
the threshold to do complete designs in MyHDL.

Finally, the existing Verilog conversion shows that "it can be done".
For me personally as a challenge, and for MyHDL, I believe I can
better work on other things, such as: "real" design work, more
HVL features, performance. In addition, adding VHDL support would be
an ideal entry point for other open-source developers, as the existing
implementation provides a clear spec and a working example.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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