[myhdl-list] Re: inout signals and cosimulation

[Jan D. <ja...@ja...>]

Terry Brown wrote:
> Hello?  I hope someone is listening :)

Sure (and thanks for using the mailing list!)

> I don't understand what is different.  Any suggestions?  I can provide 
> complete code if anyone is interested.

Looking through the code, I think the difference is the delay in the Verilog
code - probably you have run into a cosimulation restriction.

Please read the section "Restrictions" in the chapter on cosimulation
in the manual. It describes some background on the difficulties of PLI
programming and the resulting compromise. Here is a relevant quote:

"""
As explained before, co-simulated Verilog should not contain delay
statements. Ideally, there should be a run-time check to flag
non-compliant code. However, there is currently no such check in the
Icarus module.

The check can be written using the \code{cbNextSimTime} VPI callback
in Verilog. However, Icarus 0.7 doesn't support this callback. In the
meantime, support for it has been added to the Icarus development
branch.  When Icarus 0.8 is released, a check will be added.

In the mean time, just don't do this. It may appear to ``work'' but it
really won't as events will be missed over the co-simulation
interface.
"""

This seems to describe the problem that you are facing.
It's of course disturbing that the run-time check isn't there and I
will see if I can add it. However, your example got me thinking:
while it may be reasonable to disallow delays over the cosimulation
interface, it may be too severe to disallow them at all in the
Verilog - as long as Verilog doesn't run "faster" than the MyHDL side.
In that case, you could still have delayed signals internally.
What do you think?

Regards, Jan

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