[myhdl-list] inout signals and cosimulation

[Terry B. <tt...@ve...>]

Hello?  I hope someone is listening :)

I am using myhdl to provide stimulus to a verilog design that has a 
bidirectional data bus and I am having trouble understanding why myhdl 
is not seeing variable changes within the verilog simulation.

In the verilog testbench, I have done this:

wire [31:0] pp_db;
reg [31:0] pp_db_tosim;
wire [31:0] pp_db_fromsim;
assign #10 pp_db_fromsim = (pp_oe) ? 32'hbadda000 : pp_db;
reg pp_drv;
assign pp_db = (pp_drv) ? pp_db_tosim : 32'hzzzzzzzz;

initial
begin
     $from_myhdl(pp_bus_clk,pp_reset, pp_adr, pp_db_tosim, pp_cs, pp_rw, 
pp_oe, pp_blast, pp_wbe, pp_we, pp_drv);
     $to_myhdl(pp_db_fromsim, pp_db);
     $dumpvars;
end

There is, additionally, a module in the verilog design that drives the 
pp_db with a value on a read.  So, when a read is active (pp_oe is 0) 
pp_db_fromsim is assigned the pp_db value that is driven from within the 
module responding to the read.

In g2test.py, I do the following:

pp_db = Signal(intbv(0))
pp_db_fromsim = Signal(intbv(0))
pp_db_tosim = Signal(0)
print "read_ppc address: %x; data: %s; time: %d" % 
(address,pp_db_fromsim[15:0],now())
print "read_ppc address: %x; db: %s; time: %d" % (address,hex(pp_db),now())

(line wrap may make the print statements look funny, but they work.)


After simulating using myhdl to provide the stimulus, I get what I 
expect when I view the resulting vcd file with a waveform viewer. 
pp_db_fromsim changes values when the read occurs, delayed by 10 ticks 
from the change to pp_db.

the problem is that the print statements don't show any changes to 
pp_db_fromsim, although they do show the changes to pp_db.  How come?  I 
put in a yield pp_db_fromsim to catch any changes to that variable, but 
it never triggers.  Other yield statements like this do trigger.

I don't understand what is different.  Any suggestions?  I can provide 
complete code if anyone is interested.

Terry Brown