Re: [myhdl-list] Re: how to create records in MyHDL like those in VHDL

[bedros <be...@ya...>]

Jan,

I'm using version .3. The simulation seems to be
correct; and that's what matter most. I found a work
around for the composite signal types. Whatever
signals I want to see in the waveform, I would bind
them to another variable in top level so traceSignals
can find them.

I'm using a class to pass signals to different modules
and in top level I assgined those signals in the class
to a variable so theu appear in the vcd file


here's my modified code

# test record

from myhdl import *

state_t = enum('idle_st', 'load_st', 'process_st',
'exit_st')

class my_record:
    def __init__(self):
        self.A = Signal(bool(0))
        self.Bvec = Signal(intbv()[32:])
        self.state = Signal(state_t.idle_st)

#clock generator
def clk_gen(CLK, period=10):
    lowTime = int(period / 2)
    highTime = period - lowTime
    while True:
        yield delay(lowTime)
        CLK.next = 1
        yield delay(highTime)
        CLK.next = 0
        
# Reset generator        
def reset_gen(CLK, RST):
    RST.next = 1
    yield negedge(CLK)
    RST.next = 0


            

def module_cls(CLK, RST, my_record, rst_value):
    
    while True:
        yield posedge(CLK), RST
            
        if RST:
            my_record.A.next        = 0
            my_record.Bvec.next     = rst_value
            my_record.state.next    = state_t.idle_st
        else:
            my_record.A.next        = not
my_record.A.val
            my_record.Bvec.next     =
my_record.Bvec.val +1
            my_record.state.next    = state_t.load_st
            
            
def module_s_cls(CLK, RST, my_record1, my_record2):
    
    module1_u = module_cls(CLK, RST, my_record1,
0x100)
    module2_u = module_cls(CLK, RST, my_record2,
0x200)
    
    return module1_u, module2_u
            
def top():
    
    
    # CLK and RST are of boolean type
    # clock and reset signals
    CLK                     = Signal(bool(0))
    RST                     = Signal(bool(0))
    # units to generate the clock and reset
    clk_gen_u               = clk_gen(CLK)
    reset_gen_u             = reset_gen(CLK,RST)
    
    
    
    # class of signals
    my_record1_sig           = my_record()
    my_record2_sig           = my_record()
    
    sig1A               = my_record1_sig.A
    sig1Bvec            = my_record1_sig.Bvec
    sig1State           = my_record1_sig.state
    
    sig2A               = my_record2_sig.A
    sig2Bvec            = my_record2_sig.Bvec
    sig2State           = my_record2_sig.state
    
    mod_cls_u               = module_s_cls(CLK, RST, 
                                           
my_record1_sig, my_record2_sig)
    
    return clk_gen_u, reset_gen_u, mod_cls_u

def main():
    
    top_u = traceSignals(top)
    sim = Simulation(top_u)
    sim.run(100)

if __name__ == '__main__':
    main()



--- Jan Decaluwe <ja...@ja...> wrote:
> bedros wrote:
> > Thanks, Jan for you suggestions.
> > 
> > I tried combining signals using lists and classes
> and
> > and worked for simulation, but only signals
> defined at
> > top level(CLK, RST) appeared in vcd file.
> > 
> > Here's my code, so you can run it by yourself and
> > point to me what I'm doing wrong.
> 
> Nothing wrong, except expectations :-)
> Function traceSignals finds the hierarchical regions
> in a
> design, and inspect their namespaces for things of
> type Signal.
> Those are mapped to a net in the VCD output. So, it
> doesn't
> find composite types like lists of Signals, or class
> instances
> whose members are Signals. Note that VCD doesn't
> support such
> things natively either (far from it), so some kind
> of heuristic
> mapping would be needed otherwise. Given what I
> expect from
> waveforms (low level debugging before actual
> verification
> starts) this wouldn't be worth the trouble in my
> judgement.
> 
> The result is that you will only see Signals with a
> simple
> name in the VCD output. You could of course always
> do things like:
> 
> list_sig = [A, Bvec, state] =
> [Signal(bool(0)),Signal(intbv()[32:]),
> Signal(state_t.idle_st)
> 
> I did find a bug while looking at this. Do you use
> 0.3 or 0.4?
> In 0.4, the idea is that the generators at the
> lowest level
> can also be hierarchical regions in the VCD output -
> provided
> they get a name (this was not the case in 0.3).
> 
> In 0.4, function _getGens in _extractHierarchy.py is
> buggy 
> and should be as follows:
> 
> def _getGens(arg):
>     if type(arg) is GeneratorType:
>         return [arg]
>     elif type(arg) is _AlwaysComb:
>         return [arg.gen]
>     else:
>         l = []
>         for elt in arg:
>             if type(elt) is GeneratorType:
>                 l.append(elt)
>             elif type(elt) is _AlwaysComb:
>                 l.append(elt.gen)
>         return l
> 
> Regards, Jan
> 
> > 
> > 
> > 
> > # test record
> > 
> > from myhdl import *
> > 
> > state_t = enum('idle_st', 'load_st', 'process_st',
> > 'exit_st')
> > 
> > class my_record:
> >     def __init__(self):
> >         self.A = Signal(bool(0))
> >         self.Bvec = Signal(intbv()[32:])
> >         self.state = Signal(state_t.idle_st)
> > 
> > #clock generator
> > def clk_gen(CLK, period=10):
> >     lowTime = int(period / 2)
> >     highTime = period - lowTime
> >     while True:
> >         yield delay(lowTime)
> >         CLK.next = 1
> >         yield delay(highTime)
> >         CLK.next = 0
> >         
> > # Reset generator        
> > def reset_gen(CLK, RST):
> >     RST.next = 1
> >     yield negedge(CLK)
> >     RST.next = 0
> > 
> > def module_list(CLK, RST, list_sig):
> >     
> >     while True:
> >         yield posedge(CLK), RST
> >             
> >         if RST:
> >             list_sig[0].next        = 0
> >             list_sig[1].next        = 0x100
> >             list_sig[2].next        =
> state_t.idle_st
> >         else:
> >             list_sig[0].next        = not
> > list_sig[0].val
> >             list_sig[1].next        =
> list_sig[1].val
> > +1
> >             list_sig[2].next        =
> state_t.load_st
> >             
> > 
> > def module_cls(CLK, RST, my_record):
> >     
> >     while True:
> >         yield posedge(CLK), RST
> >             
> >         if RST:
> >             my_record.A.next        = 0
> >             my_record.Bvec.next     = 0x100
> >             my_record.state.next    =
> state_t.idle_st
> >         else:
> >             my_record.A.next        = not
> > my_record.A.val
> >             my_record.Bvec.next     =
> > my_record.Bvec.val +1
> >             my_record.state.next    =
> state_t.load_st
> > 
> >             
> > def top():
> >     
> >     
> >     # CLK and RST are of boolean type
> >     # clock and reset signals
> >     CLK                     = Signal(bool(0))
> >     RST                     = Signal(bool(0))
> >     # units to generate the clock and reset
> >     clk_gen_u               = clk_gen(CLK)
> >     reset_gen_u             = reset_gen(CLK,RST)
> >     
> >     # list of signals
> >     list_sig                = [Signal(bool(0)),
> > Signal(intbv()[32:]), Signal(state_t.idle_st)]
> >     mod_list_u              = module_list(CLK,
> RST,
> > list_sig)
> >     
> >     # class of signals
> >     my_record_sig           = my_record()
> >     
> >     
> >     mod_cls_u               = module_cls(CLK, RST,
> > my_record_sig)
> >     
> >     return clk_gen_u, reset_gen_u, mod_cls_u,
> > mod_list_u
> > 
> > def main():
> >     
> >     top_u = traceSignals(top)
> >     sim = Simulation(top_u)
> >     sim.run(100)
> > 
> > if __name__ == '__main__':
> >     main()
> > 
> > 
> > --- Jan Decaluwe <ja...@ja...> wrote:
> > 
> >>bedros wrote:
> >>
> >>>Jan,
> >>>
> >>>I got a question for you. I've been playing with
> >>
> >>MyHDL
> >>
> >>>whenever I have extra time. Everything works fine
> >>
> >>for
> >>
> >>>me, but I need a way to combine many signals into
> >>
> >>one
> >>
> >>>record so I can pass it around.
> >>
> >>Some up-front remarks. In VHDL, you can create a
> >>composite
> >>type and then create a signal with it. In MyHDL,
> you
> 
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