[myhdl-list] Re: how to create records in MyHDL like those in VHDL

[Jan D. <ja...@ja...>]

bedros wrote:
> Jan,
> 
> I got a question for you. I've been playing with MyHDL
> whenever I have extra time. Everything works fine for
> me, but I need a way to combine many signals into one
> record so I can pass it around.

Some up-front remarks. In VHDL, you can create a composite
type and then create a signal with it. In MyHDL, you could
do something similar (using classes), but in addition,
you can also create a composite type consisting of signals ...

An example why this is relevant, consider:

s = Signal(intbv()[8:]

then s[i] is not a Signal, but an indexed item from the
signal's current value. You could not use it to wait
on, or in structure for example. This behavior will
probably be the most important MyHDL "gotcha" for HDL
users. I found it just too hard and complicated to
implement it otherwise.

However, it's trivial to create a list of signals:

sl = [Signal(bool()) for i in range(8)]

Now sl[i] is a signal, you can wait on it, use it
ins structure etc. Note that there's no equivalent of this
in the common HDLs. I think about this capability
as the "workaround" for the "gotcha" above.

The point is that you have be careful where
to "place" the Signals in a composite type - they
should be at the level where you will need
signal "services".

> 
> I tried to create a new class with all my signals
> instantiated and it worked fine, except I needed to
> modify your source code to get the VCD waveforms. Even
> though I used __str__ attribute; I still feel that
> there should be a better way to do it. I'm new to both
> MyHDL and Python.

Using __str__ to get VCD output from a custom class seems
the right way to me. We talked about this before - perhaps
you should show me your modifications for me to understand
the problem.

One problem may be that we are struggling with VCD format
limitations. It's a low-level format with not even native
support for enums, and certainly not for composite types.

> 
> My question is how to make a record of something
> roughly like this (in vhdl)
> 
> type pkg_t is (data, address, command);
> 
> type my_record is record
> 
>      package_type   : pkg_t;
>      load           : bit_vector(31 downto 0);
>      valid          : boolean;
> 
> end record;
> 
> I can use enum for pkg_t statement, but how can I
> create the record? should I use a function, list, or a
> class?

A class would seem the obvious choice.

Assuming that you want to package signals (see above),
I would expect that something like this should work:

pkg_t = enum('data', 'address', 'command')

class my_record():
    def __init__(self):
        self.package_type = Signal(pkg_t.data)
        self.load = Signal(intbv()[32:])
        self.valid = Signal(bool())

interface = my_record()

Hope this helps, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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