[myhdl-list] Re: MyHDL question

[Jan D. <ja...@ja...>]

Frank Palazzolo wrote:
> Thanks Jan, this is just what I needed.  I will give this a try and let you
> know how it works out.
> 
> It's kind of silly, but the chip I was modelling was a simple 74LS93 4-bit
> ripple counter which has 2 clock inputs, one for Q0 and one for Q1-Q3.  It
> is possible that both clocks could appear at the same time.

In that case however, I advise you to use separate generators:

Q = Signal(intbv()[4:])

def Counter(Q, clk1, clk2, ...):

    def proc0():
        while 1:
            yield posedge(clk1)
            ...
            Q.next[0] = ....

    def proc1_3():
        while 1:
            yield posedge(clk2)
            ...
            Q.next[3:1] = ....

    return proc0(), proc1_3()

(Note that this should work as you expect in MyHDL, but in VHDL
you would get into trouble with signal resolution etc.)

> 
> My long term plan is to try to do some simulations of some old Black & White
> coin-op arcade games (like Pong, etc.), based on the schematics.  These
> games were built from about 1973-1981 and have no CPU's, only a bunch of
> discrete logic chips.  I'm going to try to enter the structural data from
> the schematics, build a small library of TTL parts, and use MyHDL & PyGame
> to try to generate screenshots.

If there's any "structure" in the structure, recall that you could use Python's
full power, to describe it: lists of instances/signals, for-loops, if's,
recursion ... MyHDL's ultra light-weight approach to structure is something
that I like in particular but haven't explored a lot yet.

> I'm sure that none of the simulations will approach "real-time", but I have
> another idea to achieve that later.
> 
> I've done something like this with structural VHDL, but IMHO Python/MyHDL is
> much nicer :)
> 
> Thanks again!
> -Frank

Regards, Jan

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