[myhdl-list] MyHDL question
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jandecaluwe
From: Frank P. <pal...@co...> - 2004-02-11 12:22:30
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Hello Jan, I've just discovered MyHDL and I am quite impressed! I have been fooling around with generators in Python with an eye toward simulation. I first discovered SimPy, and then those guys introduced me to MyHDL when I mentioned I wanted to do gate-level simulation. I am trying to do some logic simulations of old TTL designs. So far I've run into one small issue.... If I want to edge-trigger on either of two edge events, as in yield posedge(A), posedge(B) How can I tell which one has occurred after the yield, or if both have occurred? Should this be broken into two processes somehow? I realize I can check the current value of A and B - but I don't seem to have any information on the previous values of A and B when the yield was called. Some of your examples have a similar situation (clock and reset) but in those cases you don't care about the actual "edge" of reset, only the resulting level. FWIW - I am attempting to model a simple 74LS93 chip, which has two clock inputs. Thanks, Frank Palazzolo |