[myhdl-list] Re: printing vcd files for custom objects
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From: Jan D. <ja...@ja...> - 2003-11-14 21:43:15
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bedros wrote: > Jan, > > Thanks a lot for providing myhdl. I used it to model a > design and I'm very impressed. > > However, it still needs a lot of work. I made some > changes to files (_Signal.py and _traceSignal.py) to > allow printing vcd output of a custom object (class) > instead of only int and intbv. The fallback behavior for any type should be to print the string representation (from str()) as a VCD string output. I think this is the best one can do for the general case. Could you explain why it does not work for you? There are a few issues with the approach that I'm aware of: - string output is not a VCD standard feature - it is only supported by gtkwave as far as I know. Probably this means that VCD is not the appropriate solution for our purposes (we want to use arbitrary complex types as Signal values), but I used it as a proof of concept because it is so popular. LXT may the solution - it supports string output but then again I think gtkwave doesn't support that feature yet. - some string output doesn't work with gtkwave, I noticed. In particular, I believe you cannot have blanks. Note that you always have the option to specialize __str__() to fix issues for a given type. > I'm still new to python and myhdl; but I'm hoping in > couple weeks to finish testing my changes and be ready > for a release. > > for many years, I wanted to have an easy to use, > event-driven, and efficient modeling tools; Python and > myhdl seem to be the perfect fit. > > Thanks again, and if you need help in developing parts > of myhdl, I'll be happy to provide any assistance. I > have access to a vhdl simulator (active HDL) and they > claim to support PLI but I never used it and not sure > if it's fully compatible with the standards. You are more than welcome. An interface to a popular VHDL simulator would be a real value. Some remarks: - some time ago another engineer offered help to provide a cosimulation interface to VHDL. I explained the needs, also warning that this kind of development is not necessarily fun (from my experience with the Verilog PLI - though it's real fun to have it once it works.) I have not heard from him since ... - last time I checked I believe Aldec's PLI did not have the capability to write values to signals (only to read them). In that case, we don't have a solution. Keep up the good work, and let us know about it! Regards, Jan -- Jan Decaluwe - Resources bvba - http://jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Bored with EDA the way it is? Check this: http://jandecaluwe.com/Tools/MyHDL/Overview.html |