Re: [myhdl-list] ImpulseC generated VHDL files being tested by MyHDL

[Jan D. <ja...@ja...>]

David Blubaugh wrote:
> To All,
>  
>  
> I was wondering if it is feasible to utilize MyHDL and Python to develop 
> a simulation environment for VHDL files being generated by ImpulseC?  
> Such as if I develop, lets say an FIR filter is developed by ImpulseC 
> generated VHDL files.  Can I then develop a python program with MyHDL 
> to develop a simulated environment, where that particular FIR filter is 
> being utilized within lets say as a component within a wireless modem 
> operating within a Humvee in arid desert conditions?  This type of 
> simulation is known as developing a test vector.  I was wondering if 
> this is possible with Python and MyHDL? 

You cannot use MyHDL to co-simulate with VHDL, but you can use it
to develop VHDL test benches if you obey the constraints imposed by
the convertor. Read more about it here:

http://www.myhdl.org/doc/dev/0.6/whatsnew/0.6.html#conversion-of-test-benches

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org