Re: [myhdl-list] Name generation RTL components

[Jan D. <ja...@ja...>]

Jos Huisken wrote:
> 
> 
> On Sun, Oct 5, 2008 at 8:20 PM, Jan Decaluwe wrote:
> 
>     I assume that you know that the converted netlist is non-hierarchical,
>     and that, therefore, the signals names are in a flat namespace -
>     so I guess your concern is how to avoid name collision.
> 
> 
> I actually did not realize it is non-hierarchical... but it's easy to see.
> Why did you make it non-hierarchical?

Short answer
-------------
Because that was the easiest thing to do.

Long answer
-----------
The purpose of MyHDL conversion is to give designers an easy
path into their existing HDL environment.
The purpose is *not* to develop a source code to "equivalent"
source code conversion tool. (Good luck with that, btw!)

Therefore, the easiest path to conversion was chosen. The
convertor does not start from the MyHDL source code; instead,
it uses the Python interpreter as much as possible to elaborate
the design first. So it starts from the same data structure
as the simulator, and this happens to be non-hierarchical.
A flat list of generators, basically.

It is true however that some aspects of the hierarchy are tracked
anyway, in particular to give names to instances and signals.
This is done by (mis)using the Python profiler to track function
calls. The code that does this minimal task is quite hairy already;
yet this is much simpler than maintaining the original hierarchy
in the converted output.

A final note: hierarchy is very useful to humans, but no so much
to tools. Up to a few 100,000 gates, I don't think you'll have
a problem with a back-end tool. (And above that, you surely
must have enough money to hire me and improve the solution :-))

 > I would expect keeping the
 > hierarchy as specified is easy.

Not necessarily, see above.

> On the other hand I would like to control toVerilog/toVHDL w.r.t. 
> hierarchy manipulation, maybe.

Yes, a valid concern. I do this for example to keep test benches
separate from a design under test. The workaround for this is
user-defined code (using __toVerilog__ and __toVHDL__) that
defines an instantiation. When the convertor encounters this,
it stops converting and inserts the user-defined code instead.
By using conversion at various levels, you can maintain the
hierarchy as you wish.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org