Re: [myhdl-list] Small failing example

[Jan D. <ja...@ja...>]

Jos Huisken wrote:
> Attached is a small, hierarchical example failing with an xor in a 
> full-adder.
> The sensitivity list of the xor (using the ports) within the full-adder 
> is inconsistent with the used (internal) signals.
> So both simulation fails and the verilog/VHDL conversion is wrong.
> Maybe the example is somewhat artificial... maybe I do something wrong. 
> These is my first small example.

I have looked into your example. The problem is with the usage
of ports inside lists. There's good news and bad news :-):
The good news is that with internal signals (for example, in larger,
more realistic examples), similar code should work as expected.
The bad news is that I don't see a way to get this to work with
ports. This means that I propose to detect this situation and
flag it as a conversion error.

Why are ports different? 2 reasons:
- in Verilog, you can't use memories as ports
- for both VHDL and Verilog, it is probably wise to support only
the most basic, scalar, standard types for ports, to avoid issues
with subsequent back-end tools.

Note that the restrictions only apply to the very top-level ports
of the design, because only those become ports in the non-hierarchical
converted output. (BTW, this demonstrates an advantage of the
conversion approach).

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
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