Re: [myhdl-list] Small failing example

[Christopher L. F. <cf...@uc...>]

>> The sensitivity list of FA_BXOR_BXOR contains in_a and in_b. Both
>> signals
>> (well... ports) are not used in the process. Instead the -not
>> initialized-
>> signal bxor_in_input is used.
>> I expect this fails in VHDL simulation.
>> The same I see in the generated verilog.

I retract some of my early posts.  From your description (or my  
failure to read to the end of the post) I thought you were eluding to  
an issue with the hierarchy.  As you mentioned the generated Verilog /  
VHDL is incorrect.

The following MyHDL:

<c> bxor = BXor([in_a, in_b], wire_a_xor_b);
<c> ...
<c> def BXor(in_input, out_output):
<c>
<c>    @always_comb
<c>    def bxor():
<c>        var_val = 0
<c>        for i in range(len(in_input)):
<c>            var_val = var_val ^ in_input[i]
<c>        out_output.next = var_val;
<c>
<c>    return bxor

is converted to

<c> always @(in_a, in_b) begin: FA_BXOR_BXOR
<c>    integer i;
<c>    reg var_val;
<c>    var_val = 0;
<c>    for (i=0; i<2; i=i+1) begin
<c>        var_val = (var_val ^ bxor_in_input[i]);
<c>    end
<c>    wire_a_xor_b <= var_val;
<c>
<c> end

This is a relatively new feature in MyHDL (list of signals in a  
generator statement).  This will have to be looked at to see if it is  
simply a bug in the original implementation or if the approach has to  
be modified.

There are multiple ways to achieve your goals in MyHDL.  If you are  
simply looking for something to work you can use the array of  
instances instead of the list of signals.