Re: [myhdl-list] Small failing example

[Christopher F. <cf...@uc...>]

If you look at the files I sent last night I added the cosimulation. 
 The generated verilog files (from your example) compile with cver 
(Verilog simulator).  The cosimulation run but gets an exception at 
some point in the simulation (believe it is unrelated to the hierarchy 
you are concerned about).  I didn't have time to debug the cosim 
error.  I can try it with iverilog as well.

Maybe I missed it in a previous post.  What specifically in the 
generated code do you think is incorrect?  Remember, as Jan mentioned 
it creates a flat hierarchy, so when you run the toVerilog on your 
fa.py the fa.v file is all you need, that Verilog file includes 
everything, don't have to include the bxor.v file, it is in the fa.v 
file.

On Tue, 7 Oct 2008 23:02:11 +0200
  "Jos Huisken" <jos...@gm...> wrote:
> Thanks for the suggestion, indeed a typo (well, actually some lack 
>of
> understanding...)
> 
> But still, while looking at the verilog and VHDL I'm not convinced 
>the
> generated VHDL/Verilog is correct:
> 
> ----
> architecture MyHDL of fa is
> 
> signal wire_a_xor_b: std_logic;
> type t_array_bxor_in_input is array(0 to 2-1) of std_logic;
> signal bxor_in_input: t_array_bxor_in_input;
> 
> begin
> 
> 
>FA_BXOR_BXOR: process (in_a, in_b) is
>    variable var_val: std_logic;
> begin
>    var_val := '0';
>    for i in 0 to 2-1 loop
>        var_val := (var_val xor bxor_in_input(i));
>    end loop;
>    wire_a_xor_b <= var_val;
> 
> end process FA_BXOR_BXOR;
> 
> out_sum <= to_std_logic((to_boolean(wire_a_xor_b) and (not
> to_boolean(in_carry))) or ((not to_boolean(wire_a_xor_b)) and
> to_boolean(in_carry)));
> out_carry <= to_std_logic((to_boolean(in_a) and to_boolean(in_b)) or
> (to_boolean(wire_a_xor_b) and to_boolean(in_carry)));
> 
> end architecture MyHDL;
> ----
> 
> The sensitivity list of FA_BXOR_BXOR contains in_a and in_b. Both 
>signals
> (well... ports) are not used in the process. Instead the -not 
>initialized-
> signal bxor_in_input is used.
> I expect this fails in VHDL simulation.
> The same I see in the generated verilog.
> 
> 
> On Tue, Oct 7, 2008 at 2:35 AM, Christopher L. Felton 
><cf...@uc...>wrote:
> 
>> Think you had a typo in the FA testbench, it seems to work ok and 
>>the
>> verilog seems alright.
>>
>>
>>