Re: [myhdl-list] Name generation RTL components

[Jan D. <ja...@ja...>]

Jos Huisken wrote:
> I agree keeping such options out of the design code.
> Question now is how to keep the hierarchical naming correct... I do not 
> see yet how to achieve easily, being a newbie.

I assume that you know that the converted netlist is non-hierarchical,
and that, therefore, the signals names are in a flat namespace -
so I guess your concern is how to avoid name collision.

Currently, the hierarchical instance name is prepended to the original
signal name. This avoids collisions in practice, but it is of course
no hard guarantee.

What could be done is make signal naming more sophisticated by checking
for a collision during the naming procedure, and adding a unique suffix
if one is found. In practice, other issues should be tackled also, e.g.
other areas of name generation such as labels, and collisions with Verilog
and VHDL keywords.

Currently, this is all brittle although a workaround is probably easy
if there's an issue.

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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