Re: [myhdl-list] Name generation RTL components

[Jan D. <ja...@ja...>]

Jos Huisken wrote:
> Suppose you have an n-input xor gate described like:
> 
> def xor(a, z, width):
>     ....
> 
> in which 'width' specifies the number of input (length of 'a').
> Suppose you want to generate both a 3-input and 4-input xor.
> How to generate unique names? Now you can execute:
>     toVerilog,name = 'xor_3'
>     toVerilog(xor, a, z, 3)
>     toVerilog,name = 'xor_4'
>     toVerilog(xor, a, z, 4)
> 
> Maybe it is a suggestion (as opposed to toVerilog.name = 'myName') with
> verilog and/or VHDL generation to insert a name giving function in the
> definition of 'xor' itself:
> 
> def xor(a, z, width):
>     set_my_name("xor_%d" % width) # or whatever...
>     ....
> 
> This would make the name attribute superflous, I think.

A couple of comments:

As the parameter list of toVerilog/toVHDL is used for ports and
parameters, we can't use it for HDL conversion configuration.
The idea to use function attributes such as 'name' is to have
a "second level" of parametrization for this purpose. I see
this as a general, extensible mechanism, and I expect more
attributes may be added in the future. BTW, for toVHDL I
have already added another one called 'configuration_declarations'.
(See the recent what's new document for 0.6).

In general I think I prefer to keep HDL conversion configuration
options as much as possible out of the design code itself, and
this mechanism achieves that.

BTW, if you wanted to generate a series of components,
you'd probably write a for loop that sets up the desired
name in a parametrized way in the loop, so this can be
done in a quite compact way also.

Jan

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