[myhdl-list] Name generation RTL components

[Jos H. <jos...@gm...>]

Suppose you have an n-input xor gate described like:

def xor(a, z, width):
    ....

in which 'width' specifies the number of input (length of 'a').
Suppose you want to generate both a 3-input and 4-input xor.
How to generate unique names? Now you can execute:
    toVerilog,name = 'xor_3'
    toVerilog(xor, a, z, 3)
    toVerilog,name = 'xor_4'
    toVerilog(xor, a, z, 4)

Maybe it is a suggestion (as opposed to toVerilog.name = 'myName') with
verilog and/or VHDL generation to insert a name giving function in the
definition of 'xor' itself:

def xor(a, z, width):
    set_my_name("xor_%d" % width) # or whatever...
    ....

This would make the name attribute superflous, I think.

-- Jos