[myhdl-list] Good progress with lists of signals

[Jan D. <ja...@ja...>]

I think I made some good progress with lists of signals
recently. I'm quite excited about this, because I believe it
will make the VHDL/Verilog convertor much more usable.

 From user feedback it had become clear that lists of signals
conversion support was confusing and not powerful enough.
I believe that all issues have now been addressed in the
development code.

In particular:

- you an now use list (of signal) index syntax freely in generators.
If used in a generator, a Verilog memory or VHDL array will be
declared. Previously, you couldn't refer to a list member in
another generator with plain signal syntax (resulting in a confusing
"Signal not unique..." error message.) Now this should be
possible.

- in an always_comb block, lists of signals are now detected and
added to the sensitivity list. (This is not necessarily "efficient":
as soon as a list member is referred to, the whole list is added
to the sensitivity list.)

The changes have been pushed to the development repo.
Look into test/conversion/general/test_listofsigs.py for unit
tests that illustrate the functionally (trivially.)

There have been some important changes, so there may be issues.
You can help by digging out old examples that you had expected to
work, but that didn't. Also, it would be interesting to know if
you find limitations with simulators and synthesis tools. I
believe the resulting Verilog code is 2001-compliant and it
works with Icarus in my unit tests. However, cver apparently
doesn't support wire memories.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com