Re: [myhdl-list] Activation list problem along with list of signals

[Andrew L. <bs...@al...>]

Jan Decaluwe wrote:

> For conversion, I can see an issue because during source code
> manipulation the decorator needs to be stripped off, and from the
> code this seems to assume a single-line decorator. It's a MyHDL
> conversion issue.

Yep, that's exactly what it is.  Again, a better error is probably
warranted.  A "Python Syntax Error" shouldn't look the same as a "MyHDL
Python Syntax Error".  Here was the error I got and the code.

Thanks,
-a


$ python test.py
Traceback (most recent call last):
  File "test.py", line 45, in <module>
    test()
  File "test.py", line 42, in test
    ve = convert_RegisterFile()
  File "test.py", line 37, in convert_RegisterFile
    writeData0, writeAddress0, writeEnable0)
  File "/home/andrewl/local/lib/python/myhdl/_toVerilog/_convert.py", line 113, in __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "/home/andrewl/local/lib/python/myhdl/_toVerilog/_analyze.py", line 130, in _analyzeGens
    ast = compiler.parse(s)
  File "/System/Library/Frameworks/Python.framework/Versions/2.5/lib/python2.5/compiler/transformer.py", line 52, in parse
    return Transformer().parsesuite(buf)
  File "/System/Library/Frameworks/Python.framework/Versions/2.5/lib/python2.5/compiler/transformer.py", line 129, in parsesuite
    return self.transform(parser.suite(text))
  File "<string>", line 1
    registerData[0x00], registerData[0x01])
                                          ^
SyntaxError: invalid syntax



#!/usr/bin/env python

from myhdl import Signal, delay, always, instance, StopSimulation, now, traceSignals, \
    Simulation, intbv, concat, enum, now, always_comb, toVerilog, instances

def RegisterFile(gclk, grst,
                 readPort0, readPort1, readPort2,
                 readAddress0, readAddress1, readAddress2,
                 writeData0, writeAddress0, writeEnable0):

    registerData = [Signal(intbv(0)[32:]) for ii in range(2)]

    @always(readAddress0, readAddress1, readAddress2,
            registerData[0x00], registerData[0x01])
    def read():
        readPort0.next = registerData[int(readAddress0)]
        readPort1.next = registerData[int(readAddress1)]
        readPort2.next = registerData[int(readAddress2)]

    @always(gclk.posedge)
    def write():
        if writeEnable0:
            if writeAddress0 != 0:
                registerData[int(writeAddress0)].next = writeData0

    return instances()

def convert_RegisterFile():
    (gclk, grst) = [Signal(bool(0)) for ii in range(2)]
    (readPort0, readPort1, readPort2, writeData0) = [Signal(intbv(0)[32:]) for ii in range(4)]
    (readAddress0, readAddress1, readAddress2, writeAddress0) = [Signal(intbv(0)[5:]) for ii in range(4)]
    writeEnable0 = Signal(bool(0))

    rf = toVerilog(RegisterFile, gclk, grst, 
                   readPort0, readPort1, readPort2,
                   readAddress0, readAddress1, readAddress2,
                   writeData0, writeAddress0, writeEnable0)

    return instances()

def test():
    ve = convert_RegisterFile()

if __name__ == '__main__':
    test()