Re: [myhdl-list] create intbv from list of bits

[Vanheesbeke S. <Ste...@va...>]

Jan, 

>why can't you do the bit processing in a single
>generator on the bits of an input intbv?

I do some serial adders and multipliers for pipelined calculations. I
started some bottom up approach (defining an carry save adder) and then
started connecting them together: that's where the list of signals comes
in. 
I used the "from intbv to list of signals" and tried also to implement
the other way, but I don't really need it at the moment. 


>Yes, but I'd like to avoid that if possible, and I still think it is.
>A "real memory" is again an implementation concept. But the
implementation
>details may vary between target technologies, and I prefer synthesis
>tools to infer that from a generic description.

I don't mean a 'real memory' as an instance of a RAM block. I think the
generic instance is a good idea, but only use it when the python source
code uses a class that describes a memory. A list of signals can be
split in separate signals (for example reg test[3] becomes test_0,
test_1 and test[2]). 

On the other hand, it should be interesting if the converter can detect
this automatically, if not, the language drops down towards a simpler
HDL like Verilog or VHDL. 


-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of Jan
Decaluwe
Sent: woensdag 20 augustus 2008 10:23
To: myh...@li...
Subject: Re: [myhdl-list] create intbv from list of bits

Vanheesbeke Stefaan wrote:
> Thanks for the effort. Indeed the proposed functionality can be done
in
> pure modeling, I needed something to explain the question. 
> 
> Maybe I'm thinking too much in hardware when writing something in
> python. What else is a BYTE (Signal(intbv(0)[8:])) than a list of BITS
> ([Signal(bool(0)) for i in range(8)]) from a hardware point of view.

Too much hardware thinking is a general issue, also in VHDL and
certainly
in Verilog :-)

The issue you raised is valid, and I need to solve it. However, now that
you mention it, why can't you do the bit processing in a single
generator on the bits of an input intbv?

> Most of the time defining a list of signals is only a way of
describing
> connections that are held together in a single variable instead of
> defining a real memory (address, data, ...). So maybe a real memory
can
> be described in a separate class to separate it from the 'list of
> signals' behavior.

Yes, but I'd like to avoid that if possible, and I still think it is.
A "real memory" is again an implementation concept. But the
implementation
details may vary between target technologies, and I prefer synthesis
tools to infer that from a generic description.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com


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