Re: [myhdl-list] Unable to get a counter working

[Jan D. <ja...@ja...>]

Andrew Lentvorski wrote:
> Jan Decaluwe wrote:
> 
>> I don't think they do anything related to the issue that you
>> had. Try something similar with plain Python, and you'll have the
>> same issue.
> 
> Actually, I understand the Python scoping rules pretty well.  I've been 
> doing Python for a while.

Then you must agree that the unbound local error you had is
to be expected, with or without a MyHDL decorator.

> The decorator actually causes certain things to be pulled into scope, 
> somehow (presumably when it works out the activation list).  I need to 
> look at that.

I don't think so, but let us know what you find.

>> Any resemblance of MyHDL with Verilog is superficial. It's much
>> closer to VHDL. This simply reflects my opinion that Verilog
>> has some serious design flaws, such as the fact that there
>> is no separation between signals and variables. So you are
>> correct that you'll have to understand the MyHDL model
>> for effective usage.
> 
> Actually getting your thoughts about this would probably be helpful to 
> those of us coming from a Python/Verilog background.  Sort of a "design 
> philosophy" thing to help make the mental transition smoother.

I agree, and such a document isn't there yet. I believe all elements
are available, but it's all implicit and scattered over the documentation
and web site.

Jan

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