Re: [myhdl-list] create intbv from list of bits

[Jan D. <ja...@ja...>]

Vanheesbeke Stefaan wrote:
> Thanks for the effort. Indeed the proposed functionality can be done in
> pure modeling, I needed something to explain the question. 
> 
> Maybe I'm thinking too much in hardware when writing something in
> python. What else is a BYTE (Signal(intbv(0)[8:])) than a list of BITS
> ([Signal(bool(0)) for i in range(8)]) from a hardware point of view.

Too much hardware thinking is a general issue, also in VHDL and certainly
in Verilog :-)

The issue you raised is valid, and I need to solve it. However, now that
you mention it, why can't you do the bit processing in a single
generator on the bits of an input intbv?

> Most of the time defining a list of signals is only a way of describing
> connections that are held together in a single variable instead of
> defining a real memory (address, data, ...). So maybe a real memory can
> be described in a separate class to separate it from the 'list of
> signals' behavior.

Yes, but I'd like to avoid that if possible, and I still think it is.
A "real memory" is again an implementation concept. But the implementation
details may vary between target technologies, and I prefer synthesis
tools to infer that from a generic description.

Jan

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