Re: [myhdl-list] create intbv from list of bits

[Jan D. <ja...@ja...>]

Ok, list of signal issues again :-)

First of all, to be clear: what you want is easy enough to do
in pure modeling. The issue, like often, is conversion with all
its restrictions.

After thinking about it, I don't see a way to do what you want
without some kind of better support for lists of signals used
inside generators. At some point, you'll need a for loop over
all the members of the list in a single generator, to avoid
multiple drivers to a signal. (I check on multiple drivers
because synthesis wouldn't allow that anyway.)

This issue is coming up regularly so I'll try to do something
about it. I can't assess feasibility or timing just yet, but
I think I have an idea to lift the current restrictions.

The background issue is that Verilog memories have all kinds
of restrictions, so you don't want to use them unless
absolutely necessary. Currently this is enforced by a
severe restriction: you can't use list syntax in a generator
for a signal which is accessed as a plain signal in some other
generator.

It may be possible to detect whether a list is actually
referenced inside a generator, and only declare it as a Verilog
memory in that case. The result would be that everything
that works now would continue to work unchanged, but now
you would be able to use lists of signals inside
generators in general.

Jan


Vanheesbeke Stefaan wrote:
> Hi,
> 
>  
> 
> For a bit manipulation functionality, I need to split an intbv into 
> induvidual bits (a list of signals).
> 
>  
> 
> On the bits some configurable operations are done, and after this, I 
> need to create an intbv again. How can this be done in myhdl?
> 
>  
> 
> I have a testcase with a simple inverter for each bit, so you get the 
> idea :
> 
>  
> 
> First I get the induvidual bits with the GetBit() function.
> 
> The bits are processed in Function()
> 
> Then I need to stick the bits toghether again...
> 
>  
> 
> Stefaan
> 
>  
> 
>  
> 
>  
> 
> from myhdl import *
> 
>  
> 
> def Function(input_, output_):
> 
>             @always_comb
> 
>             def f():
> 
>                         output_.next = not input_
> 
>             return f
> 
>  
> 
> def Connect(In, Out):
> 
>     @always_comb
> 
>     def connect():
> 
>         Out.next = In
> 
>     return connect
> 
>  
> 
> def GetBit(input_, bit, out):
> 
>             @always_comb
> 
>             def getbit():
> 
>                         out.next = input_[bit]
> 
>             return getbit
> 
>  
> 
> def SetBit(input_, bit, out):
> 
>             @always_comb
> 
>             def setbit():
> 
>                         out.next[bit] = input_
> 
>             return setbit
> 
>            
> 
>  
> 
> def test(a, out):
> 
>  
> 
>             bits        = len(a)
> 
>             a_list      = [Signal(bool(0)) for i in range(bits)]
> 
>             result_list = [Signal(bool(0)) for i in range(bits)]
> 
>            
> 
>             retval = []
> 
>             retval.extend([GetBit(a, i, a_list[i])             for i in 
> range(bits)])
> 
>             retval.extend([Function(a_list[i], result_list[i]) for i in 
> range(bits)])
> 
>            
> 
>             #need something here to create an intbv out that is a 
> concatination of the bits in result_list
> 
>            
> 
>             #setting a bit at a time :
> 
>             #retval.extend([SetBit(result_list[i], i, out) for i in 
> range(bits)])
> 
>                         #does not work :"Signal has multiple drivers : out"
> 
>            
> 
>             #passing a single bit af an intbv :
> 
>             #retval.extend([Connect(result_list[i], out[i]) for i in 
> range(bits)])
> 
>                         #does not work : "Port is not used : out"
> 
>                         #and in the verilog description : "assign 0 = 
> retval_8_In;"
> 
>            
> 
>             return retval
> 
>            
> 
> if __name__ == "__main__":
> 
>             a   = Signal(intbv(0)[4:])
> 
>             out = Signal(intbv(0)[4:])
> 
>             toVerilog(test, a, out)
> 
>  
> 
> 
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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