Re: [myhdl-list] Unable to get a counter working

[Jan D. <ja...@ja...>]

Andrew Lentvorski wrote:
> Jan Decaluwe wrote:
>> Andrew Lentvorski wrote:
>>> Could someone please explain to me what I'm doing wrong?  I'm trying to
>>> implement what would be a basic PC counter in a microprocessor.  The
>>> stage has two def's: pc_logic which should basically just be a
>>> combinatorial adder and pc_flops which captures the state of the
>>> combinatorial logic on an edge.
>>>
>>> Why doesn't this work?  Worse, why does the one commented line throw a
>>> UboundLocalError error?
>> See Gunter's post for the answer in a MyHDL context.
>>
>> For clarity, I would like to add that the issue is conceptually not related
>> to something MyHDL-specific, but to the semantics of assignment and
>> local namespaces in Python. These work differently than in many other
>> languages and it is important to understand this clearly. See also:
>>
>>    http://www.network-theory.co.uk/docs/pytut/PythonScopesandNameSpaces.html
> 
> Thanks for the reference.  The decorator is clearly doing something 
> behind the scenes that I need to think about.

To understand what the decorators do, see here:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#creating_generators_with_decorators

I don't think they do anything related to the issue that you
had. Try something similar with plain Python, and you'll have the
same issue.

It is true however that MyHDL pushes a style in which you define
local (generator) functions inside another function (that defines
the module). So issues with Python namespaces and scopes may emerge
sooner than for other Python users.

> There's no question that a lot of my issues are stupid.  Both in terms 
> of being dumb mistakes (assigning to the variable rather than the 
> attribute) as well as due to having a faulty mental model of how MyHDL 
> works.

Nothing stupid about it, we have all gone through the same issues.
I'm convinced the Python learning curve is shorter than for many
other languages, but it's still there. Of course MyHDL adds some
additional complications, that may make things much harder.
(I'm too close to know :-))

Any resemblance of MyHDL with Verilog is superficial. It's much
closer to VHDL. This simply reflects my opinion that Verilog
has some serious design flaws, such as the fact that there
is no separation between signals and variables. So you are
correct that you'll have to understand the MyHDL model
for effective usage.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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