[myhdl-list] create intbv from list of bits

[Vanheesbeke S. <Ste...@va...>]

Hi,

 

For a bit manipulation functionality, I need to split an intbv into
induvidual bits (a list of signals). 

 

On the bits some configurable operations are done, and after this, I
need to create an intbv again. How can this be done in myhdl?

 

I have a testcase with a simple inverter for each bit, so you get the
idea : 

 

First I get the induvidual bits with the GetBit() function.

The bits are processed in Function()

Then I need to stick the bits toghether again...

 

Stefaan

 

 

 

from myhdl import *

 

def Function(input_, output_):

            @always_comb

            def f():

                        output_.next = not input_

            return f

 

def Connect(In, Out):

    @always_comb

    def connect():

        Out.next = In

    return connect

 

def GetBit(input_, bit, out):

            @always_comb

            def getbit():

                        out.next = input_[bit]

            return getbit

 

def SetBit(input_, bit, out):

            @always_comb

            def setbit():

                        out.next[bit] = input_

            return setbit

            

 

def test(a, out):

 

            bits        = len(a)

            a_list      = [Signal(bool(0)) for i in range(bits)]

            result_list = [Signal(bool(0)) for i in range(bits)]

            

            retval = []

            retval.extend([GetBit(a, i, a_list[i])             for i in
range(bits)])

            retval.extend([Function(a_list[i], result_list[i]) for i in
range(bits)])

            

            #need something here to create an intbv out that is a
concatination of the bits in result_list

            

            #setting a bit at a time : 

            #retval.extend([SetBit(result_list[i], i, out) for i in
range(bits)])

                        #does not work :"Signal has multiple drivers :
out"

            

            #passing a single bit af an intbv : 

            #retval.extend([Connect(result_list[i], out[i]) for i in
range(bits)])

                        #does not work : "Port is not used : out"

                        #and in the verilog description : "assign 0 =
retval_8_In;"

            

            return retval

            

if __name__ == "__main__":

            a   = Signal(intbv(0)[4:])

            out = Signal(intbv(0)[4:])

            toVerilog(test, a, out)