[myhdl-list] Unable to get a counter working

[Andrew L. <bs...@al...>]

Could someone please explain to me what I'm doing wrong?  I'm trying to
implement what would be a basic PC counter in a microprocessor.  The
stage has two def's: pc_logic which should basically just be a
combinatorial adder and pc_flops which captures the state of the
combinatorial logic on an edge.

Why doesn't this work?  Worse, why does the one commented line throw a
UboundLocalError error?

Thanks,
-a

Here is the code:

#!/usr/bin/env python

from myhdl import Signal, delay, always, instance, StopSimulation, now, traceSignals, \
    Simulation, intbv, concat, enum, now, always_comb, toVerilog, instances

PCSTARTADDRESS = 0x10000000

def PCStage(gclk, pc):

    pcTemp = Signal(intbv(0)[32:])
    flgPCValidTemp = Signal(bool(0))

    @always_comb
    def pc_logic():
        # WTF?  If you uncomment the next line, you get an unbound
        # local error.  Why not in pc_flops(), too?
        # print "pc:pcTemp: 0x%08x:0x%08x" % (int(pc), int(pcTemp))
        pcTemp = pc + 4
        print "pc:pcTemp: 0x%08x:0x%08x" % (int(pc), int(pcTemp))

    @always(gclk.posedge)
    def pc_flops():
        print "Capturing:", now(), hex(int(pcTemp))
        pc.next = pcTemp

    return instances()

def test_PCStage_basic_0001():
    gclk = Signal(bool(0))
    halfPeriod = delay(50)
    @always(halfPeriod)
    def drive_clock():
        gclk.next = not gclk

    gclk = Signal(bool(0))
    pc = Signal(intbv(PCSTARTADDRESS)[32:])

    pc_stage = PCStage(gclk, pc)
    
    @instance
    def stimulus():
        yield delay(1000)
        print "Stopping...", now()
        raise StopSimulation

    return instances()

def main():
    tb = traceSignals(test_PCStage_basic_0001)
    sim = Simulation(tb)
    sim.run()

if __name__ == "__main__":
    main()