Re: [myhdl-list] Wraparound addition?

[Thomas T. <tho...@de...>]

Andrew Lentvorski wrote:
> How do I add two unsigned intbv() objects such that the addition wraps 
> around?
> 
> Obviously, I can do the addition and then mask it and reassign like so:
> 
> new = (old0 + old1) & 0xffff

> However, I doubt that is going to translate to verilog properly.


The following short test code can be used to try the mask approach and
the modulo approach (suggested by Jan some weeks ago).

BTW: Some german websites say that the Verilog arithmetic is defined as
wrap around arithmetic. Therefore the implementation of the wrapping
behaviour I suggested last year and again some weeks ago, is a quite
simple simulator code modification only.

--------------------------------------
from myhdl import *


def wrap(inp,out):

    @always_comb
    def w():
        #out.next = (inp +1) & 0xffff
        out.next = (inp +1)%2**16
    return instances()

i = Signal(intbv(0)[16:])
o = Signal(intbv(0)[16:])

toVerilog(wrap,i,o)
-----------------------------------------

The results (not tested):
-----------------------------------------
// File: wrap.v
// Generated by MyHDL 0.6dev8
// Date: Mon Aug 11 09:13:15 2008

`timescale 1ns/10ps

module wrap (
    inp,
    out
);

input [15:0] inp;
output [15:0] out;
wire [15:0] out;

assign out = ((inp + 1) & 65535);

endmodule
-----------------------------------------
/ File: wrap.v
// Generated by MyHDL 0.6dev8
// Date: Mon Aug 11 09:10:13 2008

`timescale 1ns/10ps

module wrap (
    inp,
    out
);

input [15:0] inp;
output [15:0] out;
wire [15:0] out;

assign out = ((inp + 1) % (2 ** 16));

endmodule
-----------------------------------------