[myhdl-list] debugging Cosimulation with Icarus Verilog

[Günter D. <dan...@we...>]

Hi Jan,

I took some time to look into the error I am getting when doing
cosimulation with Icarus Verilog. The first test that fails in the 
myhdl/test/conversion/toVerilog folder is test1 in the 
test_always_comb.py file.

The design is the following:

def design1(a, b, p):
     def logic():
         p.next = a | b
     return always_comb(logic)


What causes the exception, which stops the simulation is that p returns 
the value 'x'. I traced the problem down and it has to do with the 
change_callback() function in the myhdl.c file. It fires too early, 
already at time step 0. Comparing that with Cver, the change_callback() 
function only fires at time step 2.

Now, the change_callback() function is registered in the 
to_myhdl_calltf() function. To avoid having the change_callback() 
function trigger already in time step 0, wouldn't it make sense to 
register it in the first readonly_callback() function. That way it would 
make sure that it does not fire in time step 0?

Guenter