[myhdl-list] Completely cryptic assertion failure
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jandecaluwe
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From: Andrew L. <bs...@al...> - 2008-08-05 06:58:29
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I eventually figured out what was wrong, but could somebody explain to
me how I should debug this? Here was the error I got:
$ python memory.py
Traceback (most recent call last):
File "memory.py", line 81, in <module>
main()
File "memory.py", line 77, in main
tb = traceSignals(basic_testbench)
File "/home/andrewl/local/lib/python/myhdl/_traceSignals.py", line 82, in __call__
h = _HierExtr(name, dut, *args, **kwargs)
File "/home/andrewl/local/lib/python/myhdl/_extractHierarchy.py", line 191, in __init__
assert id(obj) in names
AssertionError
Thanks,
-a
And here was the code that caused it:
#!/usr/bin/env python
from myhdl import Signal, delay, always, Simulation, instance, StopSimulation, now, traceSignals, intbv
def StaticRAM(gclk,
stall, readData, readByteEnable, # Outputs
read, write, address, byteEnable, writeData, #Inputs
memoryMap):
@always(gclk.posedge)
def access():
assert read == 0 or write == 0
assert byteEnable == 0 or (not byteEnable) == 0
assert readByteEnable == 0 or (not readByteEnable) == 0
if read == 1 and write == 0:
# Initiate RAM read cycle
stall.next = 0 # This signals that transaction completed
readData.next = address
readByteEnable.next = byteEnable
elif read == 0 and write == 1:
# Initiate RAM write cycle
stall.next = 0 # This signals that transaction completed
# Place values into sparse RAM
elif read == 0 and write == 0:
stall.next = 1 # Not required, but makes debugging easier
else:
raise Exception("Bus Error: Simultaneous read and write transaction requested")
return access
def basic_testbench():
memoryMap = []
gclk = Signal(bool(0))
stall = Signal(bool(0))
readData = Signal(intbv(0)[32:])
readByteEnable = Signal(intbv(0)[4:])
read = Signal(bool(0))
write = Signal(bool(0))
address = Signal(intbv(0)[32:])
byteEnable = Signal(intbv(0)[4:])
writeData = Signal(intbv(0)[32:])
ram_1 = StaticRAM(gclk,
stall, readData, readByteEnable,
read, write, address, byteEnable, writeData,
memoryMap)
halfPeriod = delay(50)
@always(halfPeriod)
def drive_clock():
gclk.next = not gclk
@instance
def stimulus():
yield delay(25)
address.next = 0xf036
readByteEnable.next = 0xf
read.next = 1
yield delay(100)
read.next = 0
yield delay(200)
print "Stopping...", now()
raise StopSimulation
# !!! This is the error !!!
return drive_clock, stimulus
# It should be
return ram_1, drive_clock, stimulus
def main():
tb = traceSignals(basic_testbench)
Simulation(tb).run()
if __name__ == "__main__":
main()
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