[myhdl-list] [myhdl_hg] toVerilog unittest errors with Icarus Verilog

[Günter D. <dan...@we...>]

Hi,

I ran the unittest test_all.py in the hg repository's 
conversion/toVerilog folder and got a bunch of errors (took out the 
traceback):

======================================================================
ERROR: test1 (test_always_comb.AlwaysCombSimulationTest)
----------------------------------------------------------------------
...
ValueError: Expected boolean value, got intbv(None) (<class
'myhdl._intbv.intbv'>)

======================================================================
ERROR: test2 (test_always_comb.AlwaysCombSimulationTest)
----------------------------------------------------------------------
...
ValueError: Expected boolean value, got intbv(None) (<class
'myhdl._intbv.intbv'>)

======================================================================
ERROR: testIncRefInc2 (test_custom.TestInc)
----------------------------------------------------------------------
...
IndexError: list index out of range

======================================================================
ERROR: testIncRefInc3 (test_custom.TestInc)
----------------------------------------------------------------------
...
IndexError: list index out of range

======================================================================
FAIL: testBinaryOps (test_signed.TestBinaryOps)
----------------------------------------------------------------------
...
AssertionError: Signal(True) != Signal(False)


Comparing that to the latest development snapshot 0.6dev8, there are
only three of these errors. All the indexing errors are new with the
latest revision in the repository.

Is that expected or has it to do that I am using Icarus Verilog the
latest development snapshot for the cosimulation? In the test cver was
used by default.


Guenter