Re: [myhdl-list] intbv.saturate, intbv.wrap

[<cf...@ie...>]

The numpy is only used for analysis (plots etc), no numpy types are used for conversion to Verilog/VHDL. The CIC filter should convert to Verilog/VHDL just haven't got to it...

-----Original Message-----

From:  "Blubaugh, David A." <dbl...@be...>
Subj:  Re: [myhdl-list] intbv.saturate, intbv.wrap
Date:  Thu Jul 10, 2008 8:35 am
Size:  2K
To:  "General discussions on MyHDL" <myh...@li...>
cc:  "Christopher L. Felton" <cf...@ie...>

 
Chris,


Please tell us as to when you have finally generated Verilog or VHDL
source code.  This sounds truly interesting to have NUMPY integrated
with the MyHDL environment.  



David


  




-----Original Message-----
From: myh...@li...
[mailto:myh...@li...] On Behalf Of
Christopher L. Felton
Sent: Thursday, July 10, 2008 8:36 AM
To: General discussions on MyHDL
Subject: Re: [myhdl-list] intbv.saturate, intbv.wrap

Attached is an example of the CIC filter without using 2's compliment
wrapping or modulus.  Adjusted the bitwidth for the maximum gain.  The
plot attached is of the frequency response of the filter, green is  
averaged input spectrum and the blue is the averaged output spectrum.   
You can see that after scaling the response is expected for a D=5 (comb
delay = 5) cic filter.  Only simulation thus far, haven't converted to
Verilog or VHDL.

Note, Because the comb filter is before the integrator (to help control
infinite gain of the integrator, hence no wrap) cannot take advantage of
inserting the decimation before the comb filter to reduced storage (#
registers) for the comb.  this could be a draw backs (depending on how
you look at it).


Also, for this implementation I had to "hack" the MyHDL space.  This is
a complete hack (just temporary to do what I wanted to do).  Also
attached are the diff's that I had to make to allow the numpy types in
the generator (?).


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