Re: [myhdl-list] intbv.saturate, intbv.wrap

[Christopher L. F. <chr...@gm...>]

Attached is an example of the CIC filter without using 2's compliment  
wrapping or modulus.  Adjusted the bitwidth for the maximum gain.  The  
plot attached is of the frequency response of the filter, green is  
averaged input spectrum and the blue is the averaged output spectrum.   
You can see that after scaling the response is expected for a D=5  
(comb delay = 5) cic filter.  Only simulation thus far, haven't  
converted to Verilog or VHDL.

Note, Because the comb filter is before the integrator (to help  
control infinite gain of the integrator, hence no wrap) cannot take  
advantage of inserting the decimation before the comb filter to  
reduced storage (# registers) for the comb.  this could be a draw  
backs (depending on how you look at it).


Also, for this implementation I had to "hack" the MyHDL space.  This  
is a complete hack (just temporary to do what I wanted to do).  Also  
attached are the diff's that I had to make to allow the numpy types in  
the generator (?).