Re: [myhdl-list] intbv.saturate, intbv.wrap

[Blubaugh, D. A. <dbl...@be...>]

That sounds exactly as to what I will need for the multidimensional FFT problem that I currently tasked with at this time.   I was also wondering, if MyHDL can handle multidimensional arrays within Python that will be generated into Verilog?  
 
 
Thanks,
 
 
David Blubaugh

________________________________

From: myh...@li... on behalf of Jan Decaluwe
Sent: Sat 6/28/2008 4:12 PM
To: myh...@li...
Subject: Re: [myhdl-list] intbv.saturate, intbv.wrap



Christopher L. Felton wrote:
> I missed the earlier discussion, but my opinion the wrap is used very
> often in DSP applications.  Any time you use an integrator (CIC, loop
> filters, etc) you frequently take advantage of the wrap.  Even FIR
> filters will often use the wrap "feature".

I suspect those DSP algorithms are not specified in Verilog/VHDL.
It wouldn't be surprizing if the specs used modulo operations -
the high-level version of a wrap. We could do this in MyHDL also,
even at the RTL level. (I have often done this in VHDL.)

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com <http://www.jandecaluwe.com/> 
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com <http://myhdl.jandecaluwe.com/> 


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