Re: [myhdl-list] intbv.saturate, intbv.wrap

[Christopher L. F. <cf...@uc...>]

Correct the DSP spec would not be in Verilog/VHDL nor would it specify  
a modulus.  The spec would call for some kind of filter or something.   
As in this discussion if the filter incorporates an integrator it  
could accumulate to infinity.  Since it can't go to infinity it needs  
some limits or be allowed to wrap.

DSP you are dealing with a frequency so the integrator will grow then  
shrink, it has a frequency response.  In most cases for a "wrap" it is  
not a modulus operation, but an intended overflow.  The accumulation  
register would be allowed to overflow with the intent that it will  
underflow (back to where you started) when you start subtracting the  
negative portion of the signal, then go back to zero.

I may be missing the point but I don't think the modulus helps in this  
case?  The wrap is intended to go positive -> negative -> positive.   
In the real algorithm it should stay positive (infinite gain).  It  
will be the implementations job to meet the spec and determine the  
number of bits required.  But people will exploit the wrap property to  
get away with less bits.  This is for the signed case (common DSP  
implementation).  Unsigned modulus would be equivalent.

I went back and read the previous posts, I agree with the conclusion  
from that discussion.  You can design for a worst case maximum and  
minimum.  Then you don't need the wrap function, it may take more bits  
but should be a more stable design.  I can't think of a reason why the  
CIC filter would require a wrap.

On Jun 28, 2008, at 2:12 PM, Jan Decaluwe wrote:

> Christopher L. Felton wrote:
>> I missed the earlier discussion, but my opinion the wrap is used very
>> often in DSP applications.  Any time you use an integrator (CIC, loop
>> filters, etc) you frequently take advantage of the wrap.  Even FIR
>> filters will often use the wrap "feature".
>
> I suspect those DSP algorithms are not specified in Verilog/VHDL.
> It wouldn't be surprizing if the specs used modulo operations -
> the high-level version of a wrap. We could do this in MyHDL also,
> even at the RTL level. (I have often done this in VHDL.)
>
> Jan
>
> -- 
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