Re: [myhdl-list] Characterstringhandling

[Jan D. <ja...@ja...>]

Thomas Traber wrote:

> I would use:
> 
>   a.next = ord("y")
>   if a == ord("y"):
> 
> But that also does not work. The verilog code looks like this:
> 
>   if ((char == ord(y))) begin
> 
> It does not seem to be Verilog syntax, is it?
> Maybe the conversion result should be
> 
>   if  ((char == 121)) begin
> 
> Would you agree?

Yes. This is the compromise that I hoped you would suggest :-) It consists
in adding support for a built-in function, something which has already
been done for a few others.

> Maybe I can supply a patch for this - but it seems to be not that easy.

It's probably much easier than some other things you did already :-)

You know what - I'll specify the patch. Don't feel obliged, but if
you will do it let me know, otherwise this serves as reminder :-)
Ideally you would use mercurial, this would be a nice test of that
flow. (See http://myhdl.jandecaluwe.com/doku.php/dev:repo)

Support for 'ord'
-----------------
* in _toVerilog.py and _toVHDL.py, look in visitCallFunc how 'int'
is handled. 'ord' will be similar.
* check whether the argument is a one-char constant string -> otherwise error
* use 'ord' on the argument to calculate the integer node value

Bonus: be more strict on which built-ins are supported
------------------------------------------------------
* in _analyze.py, look in visitCallFunc
* the test 'f in builtinObjects' now passes for any builtin - it should
only pass for builtins actually supported: (int, long, bool, len, ord ...)

Ideally:
--------
* Run the tests in test/conversion to see if nothing breaks. (Note: for
test/conversion/toVerilog, cosimulation needs to be installed. In the
other dirs in test/conversion, cosimulation is not needed, but GHDL
and either icarus or cver need to be installed - see the Makefiles.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com