Re: [myhdl-list] augmented operators

[Jan D. <ja...@ja...>]

Thomas Traber wrote:
> The MyHDL todo list had a topic 
> 
> * augmented operators
> http://myhdl.jandecaluwe.com/doku.php/dev:todo:0.6?do=show#to_do
> 
> This topic is crossed out.
> 
> But augmented operators still are causing an error.
> 
> I tried it to implement it in _Signal.py. I think it works correct in
> the simulation. I also see no reason why it should not work for the
> toVerilog conversion.
> 
> Jan, do you have any special reason not to implement it?
> Lack of time? No need?

No, I must at least have thought that it was implemented :-)

But perhaps your reference to _Signal.py gives a clue. Augmented
operators are only implemented for intbv instances, where the
meaning is obviously the same as for Python integers.

I don't see how it could be done for signals, because I want
signal assignments to be explicitly different from "variable"
assignments (that is, through the .next attribute.)

Jan

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