[myhdl-list] augmented operators

[Thomas T. <tho...@de...>]

The MyHDL todo list had a topic 

* augmented operators
http://myhdl.jandecaluwe.com/doku.php/dev:todo:0.6?do=show#to_do

This topic is crossed out.

But augmented operators still are causing an error.

I tried it to implement it in _Signal.py. I think it works correct in
the simulation. I also see no reason why it should not work for the
toVerilog conversion.

Jan, do you have any special reason not to implement it?
Lack of time? No need?


Thomas