Re: [myhdl-list] Slicing an unsigned intbv to a signed one

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:

> 
> I agree about the targeted use case, that most should design with the  
> intended functionality.  But it was also indicated that backward  
> support (if you can do it in Verilog/VHDL you can do it in MyHDL)  
> should be included.

That is still the goal.

>>>> The goal is that MyHDL should make certain things easier, while
>>>> keeping other things at least as easy as in Verilog/VHDL.
>>>>
>>>> I believe that using intbv's can avoid unsigned/signed
>>>> confusion often found in VHDL/Verilog for numeric operations.
>>>> But of course, hardware designers also have a need to access and
>>>> manipulate bit representations. I believe it's possible to make
>>>> this as easy as in VHDL/Verilog. But we may not be there yet
>>>> completely, as this case shows.
> 
>> The proposals I'm seeing do something else: they change the value of
>> the operand based on the nature of the assignment target. That is much
>> more tricky and implicit. For example, consider:
>>
>>     a = intbv(0, min=-8, max=8)
>>
>> Suppose we do sign extension based on the "sign" bit, then after
>>
>>     a[:] = 15    # '1111'
>>
>> a's value would be -1. And after:
>>
>>     a[:] = 31    # '11111'
>>
>> it would also be -1. Yet with:
>>
>>     a[:] = 23    # '10111'
>>
>> you would get a bound check error. Mm, I don't like it.
> 
> Good point, trying to add this "feature"  (Verilog/VHDL hardware type  
> support) looks like it would be too kludgy.  At this juncture do you  
> suggest the implementation be left as is?  This would be one of the  
> cases where it is not pratical to make things as easy as Verilog/ 
> VHDL? 

No, I think the OP has a point that should be solved. I just want
a more "explicit" solution (Explicit is better than implicit!)

Let's go back to the OP's use case:

a = intbv(0)[8:]
b = intbv(0, min=-8, max=8)

and he wants to assign a 4-bit slice of a to b, preserving the bit
pattern.

I propose to add a method that does sign extension in the "obvious"
way. The proper name might be extendSign() but I don't object signed():

b[:] = a[4:].signed()

Remarks:
- we don't "loose" anything against Verilog or VHDL: in those languages
you need similar casting (well, I'm not entirely sure about Verilog :-))
- you could use this in expressions, e.g. b[:] = a[4:].signed() + 1,
not just assignments
- conversion to Verilog/VHDL may be easy
- note that methods are also the way to implement operators in Python.
E.g. "not a" is just syntactic sugar for a.__invert__()

Jan

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