Re: [myhdl-list] blocking and non-blocking assignments in toVerilog code.

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Jan Decaluwe wrote:

>>This is in fact also one of my career-long battles :-) Basically, I insist that
>>HDL designers need both "variable" and "signal" semantics, also in clocked
>>processes. I agree that with languages like VHDL and MyHDL, this is easier
>>to understand, because those HDLs make a difference between "variable" and
>>"signal" objects.
> 
> Have you considered writing a book about that? I feel like there is a 
> lot that could be taught, not available through books yet and it would 
> be a good publicity for MyHDL.

Yes, I have, about this and related issues. Almost 15 years ago.
I'm serious!
Title: 'Efficient HDL synthesis'
Subtitle: 'Avoiding the pitfalls of "thinking hardware"'

I never started writing because I always thought that such a book
would be obsolete by the time it would be published. I have never
been more wrong.

However (before you start to pity me) I have done something with
those ideas which is probably more satisfactory: I co-founded
a company, Easics, in which I'm still a director. I'm quite proud
on Easics, because we have a history of design successes, even when
our methodology is not exactly mainstream.

Also, over the years I have posted about these matters on
comp.lang.verilog/vhdl, trying everything from arguments,
over irony and sarcasm, to gross insults :-)
Without much success though.

> I have to say you have put a lot of ingenuity in MyHDL and every time I 
> come back to it I learn something new.

MyHDL can be interpreted as another opportunity for me to stop whining
and do something positive with my ideas about how things ought to be.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
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