Re: [myhdl-list] Slicing an unsigned intbv to a signed one

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:

>>I have not mixed the "signed" (limits set) and the generic bit-vector in 
>>the past with MyHDL, I usually have to approach the design from a MyHDL 
>>perspective.
> 
> 
> I think that is my deficit. I am getting comfortable with Verilog and 
> having a hard time getting rid of the low level bit twiddling and 
> looking at a problem form a higher level with MyHDL.

For numeric operations, I suspect the "higher level" comes naturally.
But there may still be a legitimate need for bit-level manipulations,
and MyHDL should have an answer to that also.

The general problem is to convert some bit pattern to another,
relevant bit pattern. The case you describe is sign-extension,
but there may be others. We would have to find the truly
relevant ones, and find a way to implement them in MyHDL,
including conversion.

I'm now thinking aloud for the case you describe, sign-extension.

The ideal solution might be if we could somehow give an addional
parameter to slicing, e.g. asking for "signed" slicing instead
of the default, unsigned. But I don't see how.

Another interesting way might be to introduce methods to intbv's
at this point. We could do this like for python strings: the
methods don't modify the object in-place, but instead return a
new object with the modified value. (In MyHDL tradition,
those intbv methods would return integers.) The advantage
of this approach (as opposed to creating new functions)
is that adding new methods doesn't pollute the myhdl
namespace further.

Jan

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