Re: [myhdl-list] Slicing an unsigned intbv to a signed one
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From: Jan D. <ja...@ja...> - 2008-06-11 19:31:25
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Christopher L. Felton wrote: > I don't believe there is an easy way to do this in MyHDL. I think that is correct at the current stage. > I have found > is some cases that the Verilog way of doing thing isn't always a good > way in MyHDL. In most cases Verilog doesn't really care about the > number that the bits represent. And MyHDL is different (at least the > case when using min and max) that it is concerned with the actual > value that the bits represent. The goal is that MyHDL should make certain things easier, while keeping other things at least as easy as in Verilog/VHDL. I believe that using intbv's can avoid unsigned/signed confusion often found in VHDL/Verilog for numeric operations. But of course, hardware designers also have a need to access and manipulate bit representations. I believe it's possible to make this as easy as in VHDL/Verilog. But we may not be there yet completely, as this case shows. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Kaboutermansstraat 97, B-3000 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |