Re: [myhdl-list] Slicing an unsigned intbv to a signed one

[Günter D. <dan...@we...>]

Jan Decaluwe wrote:
> Günter Dannoritzer wrote:
...
>>
>> Setting the msb is setting the sign bit. However, that does not work in 
>> MyHDL, as the underlying data type is an integer and despite the value 
>> restriction the sign bit is not bit 3 in this case. MyHDL will just 
>> complain that the value exceeds the range.
> 
> Right, as in Python there is an "indefinite" number sign
> bits to the left.
> 
> An implication is that there is no way to make an intbv
> negative by setting some indivitual bit. To make it
> negative, you'd first have to do:
> 
> a[:] = -1
> 
> and after that, it would stay negative whatever you
> do to indivual bits.

How about if there would be an additional concat() function. Like 
concatSigned().

The difference to the concat() function would be that it considers the 
concatenated bits as signed and if the msb of the concatenation is set, 
it has the effect that value is considered negative?

For example:

 >>> a = concat('101')
 >>> print a, a.min, a.max
5 0 8

 >>> a = concatSigned('101')
 >>> print a, a.min, a.max
-3 -4 4

This would allow to simplify the creation of signed intbv from bit 
slices and could be convertible to Verilog for example. I am not that 
familiar with VHDL to know how the signed values are handled there.

Guenter